NVIDIA Tegra SoC Uncore Performance Monitoring Unit (PMU)

The NVIDIA Tegra SoC includes various system PMUs to measure key performance metrics like memory bandwidth, latency, and utilization:

  • Scalable Coherency Fabric (SCF)

  • NVLink-C2C0

  • NVLink-C2C1

  • CNVLink

  • PCIE

PMU Driver

The PMUs in this document are based on ARM CoreSight PMU Architecture as described in document: ARM IHI 0091. Since this is a standard architecture, the PMUs are managed by a common driver "arm-cs-arch-pmu". This driver describes the available events and configuration of each PMU in sysfs. Please see the sections below to get the sysfs path of each PMU. Like other uncore PMU drivers, the driver provides "cpumask" sysfs attribute to show the CPU id used to handle the PMU event. There is also "associated_cpus" sysfs attribute, which contains a list of CPUs associated with the PMU instance.

SCF PMU

The SCF PMU monitors system level cache events, CPU traffic, and strongly-ordered (SO) PCIE write traffic to local/remote memory. Please see Traffic Coverage for more info about the PMU traffic coverage.

The events and configuration options of this PMU device are described in sysfs, see /sys/bus/event_sources/devices/nvidia_scf_pmu_<socket-id>.

Example usage:

  • Count event id 0x0 in socket 0:

    perf stat -a -e nvidia_scf_pmu_0/event=0x0/
    
  • Count event id 0x0 in socket 1:

    perf stat -a -e nvidia_scf_pmu_1/event=0x0/
    

PCIE PMU

The PCIE PMU monitors all read/write traffic from PCIE root ports to local/remote memory. Please see Traffic Coverage for more info about the PMU traffic coverage.

The events and configuration options of this PMU device are described in sysfs, see /sys/bus/event_sources/devices/nvidia_pcie_pmu_<socket-id>.

Each SoC socket can support multiple root ports. The user can use "root_port" bitmap parameter to select the port(s) to monitor, i.e. "root_port=0xF" corresponds to root port 0 to 3. /sys/bus/event_sources/devices/nvidia_pcie_pmu_<socket-id>/format/root_port shows the valid bits that can be set in the "root_port" parameter.

Example usage:

  • Count event id 0x0 from root port 0 and 1 of socket 0:

    perf stat -a -e nvidia_pcie_pmu_0/event=0x0,root_port=0x3/
    
  • Count event id 0x0 from root port 0 and 1 of socket 1:

    perf stat -a -e nvidia_pcie_pmu_1/event=0x0,root_port=0x3/
    

Traffic Coverage

The PMU traffic coverage may vary dependent on the chip configuration:

  • NVIDIA Grace Hopper Superchip: Hopper GPU is connected with Grace SoC.

    Example configuration with two Grace SoCs:

    *********************************          *********************************
    * SOCKET-A                      *          * SOCKET-B                      *
    *                               *          *                               *
    *                     ::::::::  *          *  ::::::::                     *
    *                     : PCIE :  *          *  : PCIE :                     *
    *                     ::::::::  *          *  ::::::::                     *
    *                         |     *          *      |                        *
    *                         |     *          *      |                        *
    *  :::::::            ::::::::: *          *  :::::::::            ::::::: *
    *  :     :            :       : *          *  :       :            :     : *
    *  : GPU :<--NVLink-->: Grace :<---CNVLink--->: Grace :<--NVLink-->: GPU : *
    *  :     :    C2C     :  SoC  : *          *  :  SoC  :    C2C     :     : *
    *  :::::::            ::::::::: *          *  :::::::::            ::::::: *
    *     |                   |     *          *      |                   |    *
    *     |                   |     *          *      |                   |    *
    *  &&&&&&&&           &&&&&&&&  *          *   &&&&&&&&           &&&&&&&& *
    *  & GMEM &           & CMEM &  *          *   & CMEM &           & GMEM & *
    *  &&&&&&&&           &&&&&&&&  *          *   &&&&&&&&           &&&&&&&& *
    *                               *          *                               *
    *********************************          *********************************
    
    GMEM = GPU Memory (e.g. HBM)
    CMEM = CPU Memory (e.g. LPDDR5X)
    

    Following table contains traffic coverage of Grace SoC PMU in socket-A:
    +--------------+-------+-----------+-----------+-----+----------+----------+
    |              |                        Source                             |
    +              +-------+-----------+-----------+-----+----------+----------+
    | Destination  |       |GPU ATS    |GPU Not-ATS|     | Socket-B | Socket-B |
    |              |PCI R/W|Translated,|Translated | CPU | CPU/PCIE1| GPU/PCIE2|
    |              |       |EGM        |           |     |          |          |
    +==============+=======+===========+===========+=====+==========+==========+
    | Local        | PCIE  |NVLink-C2C0|NVLink-C2C1| SCF | SCF PMU  | CNVLink  |
    | SYSRAM/CMEM  | PMU   |PMU        |PMU        | PMU |          | PMU      |
    +--------------+-------+-----------+-----------+-----+----------+----------+
    | Local GMEM   | PCIE  |    N/A    |NVLink-C2C1| SCF | SCF PMU  | CNVLink  |
    |              | PMU   |           |PMU        | PMU |          | PMU      |
    +--------------+-------+-----------+-----------+-----+----------+----------+
    | Remote       | PCIE  |NVLink-C2C0|NVLink-C2C1| SCF |          |          |
    | SYSRAM/CMEM  | PMU   |PMU        |PMU        | PMU |   N/A    |   N/A    |
    | over CNVLink |       |           |           |     |          |          |
    +--------------+-------+-----------+-----------+-----+----------+----------+
    | Remote GMEM  | PCIE  |NVLink-C2C0|NVLink-C2C1| SCF |          |          |
    | over CNVLink | PMU   |PMU        |PMU        | PMU |   N/A    |   N/A    |
    +--------------+-------+-----------+-----------+-----+----------+----------+
    
    PCIE1 traffic represents strongly ordered (SO) writes.
    PCIE2 traffic represents reads and relaxed ordered (RO) writes.
    
  • NVIDIA Grace CPU Superchip: two Grace CPU SoCs are connected.

    Example configuration with two Grace SoCs:

    *******************             *******************
    * SOCKET-A        *             * SOCKET-B        *
    *                 *             *                 *
    *    ::::::::     *             *    ::::::::     *
    *    : PCIE :     *             *    : PCIE :     *
    *    ::::::::     *             *    ::::::::     *
    *        |        *             *        |        *
    *        |        *             *        |        *
    *    :::::::::    *             *    :::::::::    *
    *    :       :    *             *    :       :    *
    *    : Grace :<--------NVLink------->: Grace :    *
    *    :  SoC  :    *     C2C     *    :  SoC  :    *
    *    :::::::::    *             *    :::::::::    *
    *        |        *             *        |        *
    *        |        *             *        |        *
    *     &&&&&&&&    *             *     &&&&&&&&    *
    *     & CMEM &    *             *     & CMEM &    *
    *     &&&&&&&&    *             *     &&&&&&&&    *
    *                 *             *                 *
    *******************             *******************
    
    GMEM = GPU Memory (e.g. HBM)
    CMEM = CPU Memory (e.g. LPDDR5X)
    

    Following table contains traffic coverage of Grace SoC PMU in socket-A:
    +-----------------+-----------+---------+----------+-------------+
    |                 |                      Source                  |
    +                 +-----------+---------+----------+-------------+
    | Destination     |           |         | Socket-B | Socket-B    |
    |                 |  PCI R/W  |   CPU   | CPU/PCIE1| PCIE2       |
    |                 |           |         |          |             |
    +=================+===========+=========+==========+=============+
    | Local           |  PCIE PMU | SCF PMU | SCF PMU  | NVLink-C2C0 |
    | SYSRAM/CMEM     |           |         |          | PMU         |
    +-----------------+-----------+---------+----------+-------------+
    | Remote          |           |         |          |             |
    | SYSRAM/CMEM     |  PCIE PMU | SCF PMU |   N/A    |     N/A     |
    | over NVLink-C2C |           |         |          |             |
    +-----------------+-----------+---------+----------+-------------+
    
    PCIE1 traffic represents strongly ordered (SO) writes.
    PCIE2 traffic represents reads and relaxed ordered (RO) writes.